There are a variety of different applications that can use memory circuits including, but not limited to, programmable logic devices (PLDs). PLDs are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locked loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet, and so forth.
Each programmable tile can include both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are often programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
As the size of the configuration data used to program PLDs increases, the time required to load the configuration data can increase. Thus, the time before the PLD is fully-configured and operational can increase. This can be problematic in instances where it is desirable to have the PLD be available quickly, whether upon power-up or in similar situations. These and other problems can be problematic for PLD design and their use.